1. Field of the Invention
The present invention relates in general to an ESD device. In particular, the present invention relates to a method of forming an ESD device in a high votage while implanting ions in a low voltage well to decrease the breakdown voltage of the transistor comprising the high votage well.
2. Description of the Related Art
Electrostatic discharge (ESD) is a common phenomenon that occurs during handling of semiconductor integrated circuit (IC) devices. Electrostatic charges may accumulate and cause potentially destructive effects on an IC device. ESD stress can typically occur during a testing phase of IC fabrication, during installation of the IC onto a circuit board, as well as during use of equipment into which the IC has been installed. Damage to a single IC due to poor ESD protection in an electronic device can partially or sometimes completely hamper its operation.
There are several ESD stress models based on the reproduction of typical discharge pulses to which the IC may be exposed during manufacturing or handling. Three standards models, known as the Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM) have been proposed. The human-body model is set forth in U.S. Military Standard MIL-STD-883, Method 3015.6. The military standard models the electrostatic stress produced on an IC device when a human carrying electrostatic charges touches the lead pins of the IC device. The machine model is set forth in Industry Standard EIAJ-IC-121, which describes the electrostatic stress produced on an IC device when a machine carrying electric charges contacts the lead pins of the IC device. The charged device model describes the ESD current generated when an IC already carrying electric charges is grounded while being handled.
FIG. 1 is a block diagram according to a conventional ESD device.
The semiconductor device comprises an internal circuit 30 and I/O pad 10, and an ESD device 20 is setup between the internal circuit 30 and pad 10 to prevent ESD event.
ESD device 20 comprises MOS transistors, such as PMOS, NMOS, and CMOS transistors. FIG. 2 is a cross section of an NMOS transistor. The gate 21 and source 22 are connected to ground. Therefore, the NMOS transistor 25 is not turned on in normal operation. When ESD occurs, the built-in parasitic NPN bipolar transistor 26 in the NMOS transistor turns on the protect internal circuit 30. The source 22 constructs the emitter of the built-in parastic NPN bipolar transistor 26, the drain 23 constructs the collector of the built-in parastic NPN bipolar transistor 26, and the P-type substrate 24 constructs the base of the built-in parastic NPN bipolar transistor 26.
FIGS. 3A-3C are cross sections of a conventional ESD protection device. In FIG. 3A, substrate 40 comprises an I/O device region 40A and core device region 40B. I/O device region 40A receives higher voltage power, which is about from 3V to 6V, and core device region 40B receives lower voltage power, about from 0.8V to 1.5V. In FIG. 3B, I/O device region 40A and core device region 40B are implanted with P-type ions to form P-type well 42A and 42B, respectively. Because the power provided to the I/O device region 40A and core device region 40B are different, the doped concentration in the I/O device region 40A and core device region 40B are different. Consequently, two masks are required to dope different ion concentration in the I/O device region 40A and core device region 40B.
Next, I/O device region 40A, core device region 40B and their active areas are separated by shallow trench isolation or field insulator formed by LOCOS. Subsequent steps comprise thermal growing gate oxide layers 44A and 44B, depositing thereon a polysilicon or polycide gate layer, and then patterning the latter layer to form gate electrodes 46A and 46B for each device consisting of a gate oxide and a gate. Then using the gate 46A and 46B as masks, doped regions 48A, 481A and 48B are formed by performing ion implantation. A drive-in step is then used by heating to between about 20 to 50 minutes with the resultant lightly doped drain (LDD) structure being formed under spacers 49A and 49B as is well known in the art.
Next, an extra masking step is used to pattern the ESD devices 52A. An implant is performed, through contact opening 53 into the active regions of the ESD protection device, then N-type doped region 52A is formed. The implant has the effect of reducing the junction breakdown voltage.
After the ESD implant, the photoresist layer is removed from the substrate. Then self-aligned silicides 56A and 56B are formed over the source/drain regions 48A and 48B, and gate 46A and 46B. It is preferred that the silicides 56A and 56B are formed by silicidation of tungsten from tungsten silicide.
However, the additional masks and implantation are used while forming the ESD protection device, which will increase the cost of the process and complicate the fabricating process.
The object of the present invention is to provide a method for fabricating an ESD device with dual voltage process. The low voltage well is implanted with ions to form an ESD device when the high voltage well is implanted with ions. Therefore, the ESD device having doped concentration higher than that of low voltage well is formed without adding another mask and ion implantation to decrease the cost and the complexity of the process.
To achieve the above-mentioned object, the present invention provides a method for fabricating an ESD device, which comprises the following steps. First, a substrate undergoes first ion implantation to form a first first-type well comprising an electrostatic discharge region. Next, a second implantation is performed on the substrate and the electrostatic discharge region to form a second first-type well and an ESD device. Finally, gates, sources, and drains are formed to complete the process.